409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b add...

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Hauptverfasser: Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, McMurchie, L., Sechen, C.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
Clocks
CMOS logic circuits
Delay
Fabrication
Microprocessors
Pulse inverters
Sun
Switches
Very large scale integration
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Beschreibung
Zusammenfassung:We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels.
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2005.2