Low voltage test in place of fast clock in DDSI delay test
By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the cau...
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| creator | Haihua Yan Gefu Xu Singh, A.D. |
| description | By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method. |
| doi_str_mv | 10.1109/ISQED.2005.75 |
| format | Conference Proceeding |
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Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.</description><identifier>ISSN: 1948-3287</identifier><identifier>ISBN: 9780769523019</identifier><identifier>ISBN: 0769523013</identifier><identifier>EISSN: 1948-3295</identifier><identifier>DOI: 10.1109/ISQED.2005.75</identifier><language>eng</language><publisher>IEEE</publisher><subject>ATE ; Circuit faults ; Circuit testing ; Clocks ; defect ; Delay effects ; delay test ; Design for testability ; Fault detection ; Low voltage ; low voltage test ; Performance evaluation ; Pins ; Signal generators</subject><ispartof>Sixth international symposium on quality electronic design (isqed'05), 2005, p.316-320</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1410602$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1410602$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Haihua Yan</creatorcontrib><creatorcontrib>Gefu Xu</creatorcontrib><creatorcontrib>Singh, A.D.</creatorcontrib><title>Low voltage test in place of fast clock in DDSI delay test</title><title>Sixth international symposium on quality electronic design (isqed'05)</title><addtitle>ISQED</addtitle><description>By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.</description><subject>ATE</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Clocks</subject><subject>defect</subject><subject>Delay effects</subject><subject>delay test</subject><subject>Design for testability</subject><subject>Fault detection</subject><subject>Low voltage</subject><subject>low voltage test</subject><subject>Performance evaluation</subject><subject>Pins</subject><subject>Signal generators</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>9780769523019</isbn><isbn>0769523013</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9jEtLw0AURgcfYK1dunIzfyDxzvPOuJOmaiAgUl2XyeSORKMpTaj031utuPrgfIfD2KWAXAjw1-XyaVHkEsDkaI7YRHjtMiW9OWYzjw7QeiMVCH_y_zk8Y-fD8AagjUE3YTdV_8W3fTeGV-IjDSNvP_m6C5F4n3gKexC7Pr7_4KJYlryhLux-zQt2mkI30Oxvp-zlbvE8f8iqx_tyfltlrUAzZkm4YAJJsNgodJYwWW8jaB2NpBpDTbXWtoHUSA9owKfoVA0WSNtYk5qyq0O3JaLVetN-hM1uJbTYK1J9A2GrR0s</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Haihua Yan</creator><creator>Gefu Xu</creator><creator>Singh, A.D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>Low voltage test in place of fast clock in DDSI delay test</title><author>Haihua Yan ; Gefu Xu ; Singh, A.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f18a5ae2067d3786e7f696c044c52eb7abeb446d0fd2907509fc83b060e46cbe3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>ATE</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Clocks</topic><topic>defect</topic><topic>Delay effects</topic><topic>delay test</topic><topic>Design for testability</topic><topic>Fault detection</topic><topic>Low voltage</topic><topic>low voltage test</topic><topic>Performance evaluation</topic><topic>Pins</topic><topic>Signal generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Haihua Yan</creatorcontrib><creatorcontrib>Gefu Xu</creatorcontrib><creatorcontrib>Singh, A.D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Haihua Yan</au><au>Gefu Xu</au><au>Singh, A.D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low voltage test in place of fast clock in DDSI delay test</atitle><btitle>Sixth international symposium on quality electronic design (isqed'05)</btitle><stitle>ISQED</stitle><date>2005</date><risdate>2005</risdate><spage>316</spage><epage>320</epage><pages>316-320</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>9780769523019</isbn><isbn>0769523013</isbn><abstract>By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.</abstract><pub>IEEE</pub><doi>10.1109/ISQED.2005.75</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1948-3287 |
| ispartof | Sixth international symposium on quality electronic design (isqed'05), 2005, p.316-320 |
| issn | 1948-3287 1948-3295 |
| language | eng |
| recordid | cdi_ieee_primary_1410602 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | ATE Circuit faults Circuit testing Clocks defect Delay effects delay test Design for testability Fault detection Low voltage low voltage test Performance evaluation Pins Signal generators |
| title | Low voltage test in place of fast clock in DDSI delay test |
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