Design of the spaghetti logic parallel processor

The design and implementation of the spaghetti logic parallel processor (SLOPP), a custom CMOS, SIMD array processor, is described. The data path has been optimized for the Sobel edge detection algorithm resulting in a substantial speedup over similar architectures such as the massively parallel processor and the geometric arithmetic parallel processor. Advantages of SLOPP include the ability for diagonal transfers and its execution speed. Fabricated chips were functional at a clock rate of 50 MHz. Thus, SLOPP is at least a factor of two faster than machines such as GAPP. The project demonstrates that fast, efficient, special purpose processors can be rapidly designed and implemented by relatively inexperienced engineers.< >