Novel program versus disturb window characterization for split-gate flash cell

A new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively...

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Veröffentlicht in:	IEEE electron device letters 2005-03, Vol.26 (3), p.194-196
Hauptverfasser:	Hung-Cheng Sung, Tan Fu Lei, Te-Hsun Hsu, Ya-Chen Kao, Yung-Tao Lin, Wang, C.S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bias Devices Disturb Electronics Exact sciences and technology Flash memory Gates Hot carrier injection Integrated circuits Integrated circuits by function (including memories and processors) Methodology Nonvolatile memory operation window Optimization Physics program Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Split gate flash memory cells split-gate Stress Tolerances Tunneling Voltage Windows (intervals)
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Beschreibung
Zusammenfassung:	A new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-μm triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2004.842643