A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 /spl mu/m digital CMOS

A 12 bit pipeline ADC fabricated in a 0.18 /spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2V/sub P-P/ signal swing is applied. The occupied silicon area is 0.86 mm/sup 2/ and the power consumption equals 97 mW. A switched capacitor bias current circuit scales the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.