Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

This work evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled system on chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate quality of service (QoS). A realistic examp...

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Bibliographische Detailangaben
Hauptverfasser: Smit, L.T., Smit, G.J.M., Hurink, J.L., Broersma, H., Paulusma, D., Wolkotte, P.T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application software
Computer architecture
Computer science
Energy consumption
Energy efficiency
Mathematics
Network-on-a-chip
Runtime
System-on-a-chip
Tiles
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Beschreibung
Zusammenfassung:This work evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled system on chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate quality of service (QoS). A realistic example is mapped using this algorithm.
DOI:10.1109/FPT.2004.1393315