An economic analysis and ROI model for nanometer test
This work describes an economic and return-on-investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition...
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creator | Keller, B. Tegethoff, M. Bartenstein, T. Chickermane, V. |
description | This work describes an economic and return-on-investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model. |
doi_str_mv | 10.1109/TEST.2004.1386988 |
format | Conference Proceeding |
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We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. 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Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model.</description><subject>Applied sciences</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Costs</subject><subject>Delay effects</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Frequency</subject><subject>Geometry</subject><subject>Leakage current</subject><subject>Logic devices</subject><subject>Manufacturing</subject><subject>Semiconductor device testing</subject><subject>Testing, measurement, noise and reliability</subject><isbn>0780385802</isbn><isbn>9780780385801</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1LAzEQxQMiqLV_gHjJxeOuM8nmY4-lVC0UCrqeS5pMILIfZbOX_vcurOBc5vHej4E3jD0hlIhQvza7r6YUAFWJ0ura2hv2AMaCtMqCuGPrnH9gHllrrdU9U5uekx_6oUueu96115zyLAL_PO55NwRqeRxG3rsZoYlGPlGeHtltdG2m9d9ese-3XbP9KA7H9_12cyiSADUVSolw1lp4EwMSRqiiIYsBXW1rF00ldADlZ0M5QuGVMKTPQaMnD04YuWIvy92Ly961cXS9T_l0GVPnxusJrZY4N5m554VLRPQfLx-Qv71nUB4</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Keller, B.</creator><creator>Tegethoff, M.</creator><creator>Bartenstein, T.</creator><creator>Chickermane, V.</creator><general>IEEE</general><general>International Test Conference</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>An economic analysis and ROI model for nanometer test</title><author>Keller, B. ; Tegethoff, M. ; Bartenstein, T. ; Chickermane, V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i205t-552db662c7fd1e1f04f7e81d1a989af7426d05c1d15ae12c527e6bd61cec0a273</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Costs</topic><topic>Delay effects</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Frequency</topic><topic>Geometry</topic><topic>Leakage current</topic><topic>Logic devices</topic><topic>Manufacturing</topic><topic>Semiconductor device testing</topic><topic>Testing, measurement, noise and reliability</topic><toplevel>online_resources</toplevel><creatorcontrib>Keller, B.</creatorcontrib><creatorcontrib>Tegethoff, M.</creatorcontrib><creatorcontrib>Bartenstein, T.</creatorcontrib><creatorcontrib>Chickermane, V.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Keller, B.</au><au>Tegethoff, M.</au><au>Bartenstein, T.</au><au>Chickermane, V.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An economic analysis and ROI model for nanometer test</atitle><btitle>2004 International Conferce on Test</btitle><stitle>TEST</stitle><date>2004</date><risdate>2004</risdate><spage>518</spage><epage>524</epage><pages>518-524</pages><isbn>0780385802</isbn><isbn>9780780385801</isbn><abstract>This work describes an economic and return-on-investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model.</abstract><cop>Piscataway NJ</cop><cop>Washington DC</cop><pub>IEEE</pub><doi>10.1109/TEST.2004.1386988</doi><tpages>7</tpages></addata></record> |
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subjects | Applied sciences Circuit faults Circuit testing Costs Delay effects Electronics Exact sciences and technology Frequency Geometry Leakage current Logic devices Manufacturing Semiconductor device testing Testing, measurement, noise and reliability |
title | An economic analysis and ROI model for nanometer test |
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