Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature V/sub t/ drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature V/sub t/ drift is significantly decreased by using bottom oxide (BOX) with the thickness...

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Veröffentlicht in:IEEE electron device letters 2005-01, Vol.26 (1), p.35-37
Hauptverfasser: Roizin, Y., Pikhay, E., Gutman, M.
Format: Artikel
Sprache:eng
Schlagworte:
Charge carrier processes
Current measurement
Kinetic theory
NROM
Oxidation
oxide-nitride-oxide (ONO)
Poles and towers
reliability
silicon-oxide-nitride-oxide-silicon (SONOS) memory
SONOS devices
Stress
Temperature measurement
Threshold voltage
Tunneling
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Beschreibung
Zusammenfassung:In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature V/sub t/ drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature V/sub t/ drift is significantly decreased by using bottom oxide (BOX) with the thickness T/sub BOX/
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2004.840711