Reliability properties of low-voltage ferroelectric capacitors and memory arrays
We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (
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| Veröffentlicht in: | IEEE transactions on device and materials reliability 2004-09, Vol.4 (3), p.436-449 |
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| creator | Rodriguez, J.A. Remack, K. Boku, K. Udayakumar, K.R. Aggarwal, S. Summerfelt, S.R. Celii, F.G. Martin, S. Hall, L. Taylor, K. Moise, T. McAdams, H. McPherson, J. Bailey, R. Fox, G. Depner, M. |
| description | We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage ( |
| doi_str_mv | 10.1109/TDMR.2004.837210 |
| format | Magazinearticle |
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Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.</description><identifier>ISSN: 1530-4388</identifier><identifier>EISSN: 1558-2574</identifier><identifier>DOI: 10.1109/TDMR.2004.837210</identifier><identifier>CODEN: ITDMA2</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Arrays ; Bit distribution ; Capacitors ; CMOS logic circuits ; CMOS process ; Degradation ; Durability ; fatigue ; Ferroelectric films ; Ferroelectric materials ; ferroelectric memory ; Ferroelectricity ; FRAM ; imprint ; Logic ; Logic arrays ; Low voltage ; MOCVD ; polarization ; PZT ; retention ; Switching ; Temperature</subject><ispartof>IEEE transactions on device and materials reliability, 2004-09, Vol.4 (3), p.436-449</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c450t-5608f47037a2844ec0f5131628533b739a6fdfce824de896545061abd04386ad3</citedby><cites>FETCH-LOGICAL-c450t-5608f47037a2844ec0f5131628533b739a6fdfce824de896545061abd04386ad3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1369206$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>780,784,796,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1369206$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rodriguez, J.A.</creatorcontrib><creatorcontrib>Remack, K.</creatorcontrib><creatorcontrib>Boku, K.</creatorcontrib><creatorcontrib>Udayakumar, K.R.</creatorcontrib><creatorcontrib>Aggarwal, S.</creatorcontrib><creatorcontrib>Summerfelt, S.R.</creatorcontrib><creatorcontrib>Celii, F.G.</creatorcontrib><creatorcontrib>Martin, S.</creatorcontrib><creatorcontrib>Hall, L.</creatorcontrib><creatorcontrib>Taylor, K.</creatorcontrib><creatorcontrib>Moise, T.</creatorcontrib><creatorcontrib>McAdams, H.</creatorcontrib><creatorcontrib>McPherson, J.</creatorcontrib><creatorcontrib>Bailey, R.</creatorcontrib><creatorcontrib>Fox, G.</creatorcontrib><creatorcontrib>Depner, M.</creatorcontrib><title>Reliability properties of low-voltage ferroelectric capacitors and memory arrays</title><title>IEEE transactions on device and materials reliability</title><addtitle>TDMR</addtitle><description>We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.</description><subject>Arrays</subject><subject>Bit distribution</subject><subject>Capacitors</subject><subject>CMOS logic circuits</subject><subject>CMOS process</subject><subject>Degradation</subject><subject>Durability</subject><subject>fatigue</subject><subject>Ferroelectric films</subject><subject>Ferroelectric materials</subject><subject>ferroelectric memory</subject><subject>Ferroelectricity</subject><subject>FRAM</subject><subject>imprint</subject><subject>Logic</subject><subject>Logic arrays</subject><subject>Low voltage</subject><subject>MOCVD</subject><subject>polarization</subject><subject>PZT</subject><subject>retention</subject><subject>Switching</subject><subject>Temperature</subject><issn>1530-4388</issn><issn>1558-2574</issn><fulltext>true</fulltext><rsrctype>magazinearticle</rsrctype><creationdate>2004</creationdate><recordtype>magazinearticle</recordtype><sourceid>RIE</sourceid><recordid>eNqNkc1LAzEQxRdRsFbvgpfFg562TpJNNjlK_YSKUuo5pNlZSdk2Ndkq_e9NWUHwIMLAzOH3hvd4WXZKYEQIqKvZzdN0RAHKkWQVJbCXDQjnsqC8Kvd3N4OiZFIeZkcxLgCIqrgYZC9TbJ2Zu9Z123wd_BpD5zDmvslb_1l8-LYzb5g3GILHFm0XnM2tWRvrOh9iblZ1vsSlD9vchGC28Tg7aEwb8eR7D7PXu9vZ-KGYPN8_jq8nhS05dAUXIJuyAlYZKssSLTScMCKo5IzNK6aMaOrGoqRljVIJnlSCmHkNKYQwNRtml_3fZPp9g7HTSxcttq1Zod9ErYAIlYYn8uJPkkpJK_gXyGVyCAk8_wUu_CasUlytKKFMAFUJgh6ywccYsNHr4JYmbDUBvatM7yrTu8p0X1mSnPUSh4g_OBOKgmBf1D2RPA</recordid><startdate>20040901</startdate><enddate>20040901</enddate><creator>Rodriguez, J.A.</creator><creator>Remack, K.</creator><creator>Boku, K.</creator><creator>Udayakumar, K.R.</creator><creator>Aggarwal, S.</creator><creator>Summerfelt, S.R.</creator><creator>Celii, F.G.</creator><creator>Martin, S.</creator><creator>Hall, L.</creator><creator>Taylor, K.</creator><creator>Moise, T.</creator><creator>McAdams, H.</creator><creator>McPherson, J.</creator><creator>Bailey, R.</creator><creator>Fox, G.</creator><creator>Depner, M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7QQ</scope><scope>8BQ</scope><scope>JG9</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20040901</creationdate><title>Reliability properties of low-voltage ferroelectric capacitors and memory arrays</title><author>Rodriguez, J.A. ; Remack, K. ; Boku, K. ; Udayakumar, K.R. ; Aggarwal, S. ; Summerfelt, S.R. ; Celii, F.G. ; Martin, S. ; Hall, L. ; Taylor, K. ; Moise, T. ; McAdams, H. ; McPherson, J. ; Bailey, R. ; Fox, G. ; Depner, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c450t-5608f47037a2844ec0f5131628533b739a6fdfce824de896545061abd04386ad3</frbrgroupid><rsrctype>magazinearticle</rsrctype><prefilter>magazinearticle</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Arrays</topic><topic>Bit distribution</topic><topic>Capacitors</topic><topic>CMOS logic circuits</topic><topic>CMOS process</topic><topic>Degradation</topic><topic>Durability</topic><topic>fatigue</topic><topic>Ferroelectric films</topic><topic>Ferroelectric materials</topic><topic>ferroelectric memory</topic><topic>Ferroelectricity</topic><topic>FRAM</topic><topic>imprint</topic><topic>Logic</topic><topic>Logic arrays</topic><topic>Low voltage</topic><topic>MOCVD</topic><topic>polarization</topic><topic>PZT</topic><topic>retention</topic><topic>Switching</topic><topic>Temperature</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Rodriguez, J.A.</creatorcontrib><creatorcontrib>Remack, K.</creatorcontrib><creatorcontrib>Boku, K.</creatorcontrib><creatorcontrib>Udayakumar, K.R.</creatorcontrib><creatorcontrib>Aggarwal, S.</creatorcontrib><creatorcontrib>Summerfelt, S.R.</creatorcontrib><creatorcontrib>Celii, F.G.</creatorcontrib><creatorcontrib>Martin, S.</creatorcontrib><creatorcontrib>Hall, L.</creatorcontrib><creatorcontrib>Taylor, K.</creatorcontrib><creatorcontrib>Moise, T.</creatorcontrib><creatorcontrib>McAdams, H.</creatorcontrib><creatorcontrib>McPherson, J.</creatorcontrib><creatorcontrib>Bailey, R.</creatorcontrib><creatorcontrib>Fox, G.</creatorcontrib><creatorcontrib>Depner, M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Ceramic Abstracts</collection><collection>METADEX</collection><collection>Materials Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on device and materials reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rodriguez, J.A.</au><au>Remack, K.</au><au>Boku, K.</au><au>Udayakumar, K.R.</au><au>Aggarwal, S.</au><au>Summerfelt, S.R.</au><au>Celii, F.G.</au><au>Martin, S.</au><au>Hall, L.</au><au>Taylor, K.</au><au>Moise, T.</au><au>McAdams, H.</au><au>McPherson, J.</au><au>Bailey, R.</au><au>Fox, G.</au><au>Depner, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Reliability properties of low-voltage ferroelectric capacitors and memory arrays</atitle><jtitle>IEEE transactions on device and materials reliability</jtitle><stitle>TDMR</stitle><date>2004-09-01</date><risdate>2004</risdate><volume>4</volume><issue>3</issue><spage>436</spage><epage>449</epage><pages>436-449</pages><issn>1530-4388</issn><eissn>1558-2574</eissn><coden>ITDMA2</coden><abstract>We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TDMR.2004.837210</doi><tpages>14</tpages></addata></record> |
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| subjects | Arrays Bit distribution Capacitors CMOS logic circuits CMOS process Degradation Durability fatigue Ferroelectric films Ferroelectric materials ferroelectric memory Ferroelectricity FRAM imprint Logic Logic arrays Low voltage MOCVD polarization PZT retention Switching Temperature |
| title | Reliability properties of low-voltage ferroelectric capacitors and memory arrays |
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