A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL
In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the cu...
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| creator | Chen, T. Geens, P. Van der Plas, G. Dehaene, W. Gielen, G. |
| description | In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/. |
| doi_str_mv | 10.1109/ESSCIR.2004.1356644 |
| format | Conference Proceeding |
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The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.</description><identifier>ISBN: 0780384806</identifier><identifier>ISBN: 9780780384804</identifier><identifier>DOI: 10.1109/ESSCIR.2004.1356644</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; CMOS technology ; Delay ; Frequency synchronization ; Latches ; Programmable logic arrays ; Sampling methods ; Signal design ; Switches ; Wires</subject><ispartof>Proceedings of the 30th European Solid-State Circuits Conference, 2004, p.167-170</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1356644$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1356644$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chen, T.</creatorcontrib><creatorcontrib>Geens, P.</creatorcontrib><creatorcontrib>Van der Plas, G.</creatorcontrib><creatorcontrib>Dehaene, W.</creatorcontrib><creatorcontrib>Gielen, G.</creatorcontrib><title>A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL</title><title>Proceedings of the 30th European Solid-State Circuits Conference</title><addtitle>ESSCIR</addtitle><description>In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.</description><subject>Clocks</subject><subject>CMOS technology</subject><subject>Delay</subject><subject>Frequency synchronization</subject><subject>Latches</subject><subject>Programmable logic arrays</subject><subject>Sampling methods</subject><subject>Signal design</subject><subject>Switches</subject><subject>Wires</subject><isbn>0780384806</isbn><isbn>9780780384804</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj11LwzAYRgMiqHO_YDf5A6lvmjQfN0Kp0xU6B1avR9K-0Yw5pMkQ_fUO3HNzLg4ceAhZcCg4B3u37PumfSlKAFlwUSkl5QW5AW1AGGlAXZF5Sjs4TVhVWXlN7mvKJfMxUy6ArVe_tFlvejocpwkPmaWMOMXDO32oG_od8wd14-6YsvN7pO1zd0sug9snnJ85I2-Py9dmxbrNU9vUHYtcV5npUIFBVLo0FoIIofRKh1KNaMFzPNlqHCUMRguNwjvjuFeDt2hLBYMGMSOL_25ExO3XFD_d9LM9XxR_vadEnw</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Chen, T.</creator><creator>Geens, P.</creator><creator>Van der Plas, G.</creator><creator>Dehaene, W.</creator><creator>Gielen, G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2004</creationdate><title>A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL</title><author>Chen, T. ; Geens, P. ; Van der Plas, G. ; Dehaene, W. ; Gielen, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7f508ee672890f3ff2b67f26de90b1ef505dd40c8737e3ba8a1b6cb9e9260c703</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Clocks</topic><topic>CMOS technology</topic><topic>Delay</topic><topic>Frequency synchronization</topic><topic>Latches</topic><topic>Programmable logic arrays</topic><topic>Sampling methods</topic><topic>Signal design</topic><topic>Switches</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Chen, T.</creatorcontrib><creatorcontrib>Geens, P.</creatorcontrib><creatorcontrib>Van der Plas, G.</creatorcontrib><creatorcontrib>Dehaene, W.</creatorcontrib><creatorcontrib>Gielen, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, T.</au><au>Geens, P.</au><au>Van der Plas, G.</au><au>Dehaene, W.</au><au>Gielen, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL</atitle><btitle>Proceedings of the 30th European Solid-State Circuits Conference</btitle><stitle>ESSCIR</stitle><date>2004</date><risdate>2004</risdate><spage>167</spage><epage>170</epage><pages>167-170</pages><isbn>0780384806</isbn><isbn>9780780384804</isbn><abstract>In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows a significant reduction of the chip area. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The spurious-free dynamic range is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard 1P5M 0.25-/spl mu/m CMOS technology. The area of the current source block is 1 mm/sup 2/, and the whole core area is only 3.5 mm/sup 2/.</abstract><pub>IEEE</pub><doi>10.1109/ESSCIR.2004.1356644</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks CMOS technology Delay Frequency synchronization Latches Programmable logic arrays Sampling methods Signal design Switches Wires |
| title | A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL |
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