A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform

A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 5...

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Hauptverfasser:	LEE, Kangmin, LEE, Se-Joong, KIM, Sung-Eun, CHOI, Hye-Mi, KIM, Donghyun, KIM, Sunyoung, LEE, Min-Wuk, YOO, Hoi-Jun
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Bandwidth Clocks Delay Design. Technologies. Operation analysis. Testing Electronics Energy consumption Exact sciences and technology Fabrics Integrated circuits Network-on-a-chip Quality of service Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switches Tiles Wires
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Beschreibung
Zusammenfassung:	A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.
ISSN:	0193-6530 2376-8606
DOI:	10.1109/ISSCC.2004.1332639