Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including...

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Bibliographische Detailangaben
Hauptverfasser: Takayanagi, T., Shin, J.L., Su, J., Leon, A.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer applications
Computer networks
Coupling circuits
Microprocessors
Negative bias temperature instability
Niobium compounds
Process design
Random access memory
Titanium compounds
Yarn
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Beschreibung
Zusammenfassung:A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.
DOI:10.1109/ICICDT.2004.1309933