Modeling and calibrating an on chip vision system with a CMOS retina

This paper, a new processing architecture approach for a vision system on chip (SoC) is presented. It highlights a compromise between versatility, parallelism, processing speed and resolution. This enables to increase the system performances. The approach consists to set operators, usually integrated close in the pixels, at the array edge. Consequently, the operator's functions are shared by a group of pixels, and the image processing is then carried out sequentially. This architecture results in a pixels array associated to a mixed analog-digital processors vector. Each processor is able to carry out, in situ, a wide range of low-level image processing algorithms. A digital processor can then process the low-level information. A silicon retina is an image sensor in which analog/digital signal processing circuits are integrated in the image-sensing element or at the edge of the image sensor array to achieve some simple low-level image processing. Their key features are their capability to enable massively parallel computations with rather low power consumption. The aim when integrating such a processor, next to image sensor in a single circuit, is to increase the pixel's Fill Factor and to remove the input output bottleneck between the sensor and the digital processor.