Challenges of thermomechanical design and modeling of ultra fine-pitch wafer level packages

With the relentless trend towards ever increasing number of I/Os of IC chips, the pitch of chip-to-substrate interconnections are ever decreasing. As the pitch is decreased so also will be the stand-off. If the coefficient of the thermal expansion of the chip and substrate remains the same, and the...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Tay, A.A.O.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitive sensors Fatigue Packaging Semiconductor device modeling Silicon Temperature distribution Thermal expansion Thermal stresses Thermomechanical processes Wafer scale integration
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