Challenges of thermomechanical design and modeling of ultra fine-pitch wafer level packages

With the relentless trend towards ever increasing number of I/Os of IC chips, the pitch of chip-to-substrate interconnections are ever decreasing. As the pitch is decreased so also will be the stand-off. If the coefficient of the thermal expansion of the chip and substrate remains the same, and the temperature cycling range remains the same, the stresses and strains induced in the interconnections will increase dramatically. This will probably decrease the fatigue life of the interconnections to an unacceptably low level unless novel designs and materials can be produced to address the problem. This paper describes the challenges in the design and thermomechanical modeling of the reliability of next generation ultra fine-pitch wafer level packages. Three designs of interconnections at 100 /spl mu/m pitch for 20 mm/spl times/20 mm wafer level packages are proposed and modeled. Two thermomechanical modeling approaches, namely, the equivalent beam approach and the small sector approach, have been developed to perform the the effective modeling of 40,000 interconnections per package. It was found that the key parameter is the coefficient of thermal expansion of the board which has to be made to match closer to that of the silicon chip in order to meet current reliability standards.