Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

The low fatigue resistance of solder joints limits the reliability of many types of electronic packages. In this study, the reliability of a wafer level package (WLP) was optimized by introducing a flexible silicone bump between the solder joint and the chip in order to buffer the strains and stresses in the solder during thermal cycling. Silicones are non-conductive materials and therefore a metal layer must be applied over the silicone bump for electrical conductivity. The reliability of the package was optimized by balancing the reliability of the solder joint with that of the metallization. The thermomechanical behavior of the eutectic SnPb solder joints and copper metallization was analyzed using a non-linear 3D finite element model (FEM) and accelerated thermal test cycles. Failure analysis after traditional reliability tests of an actual wafer level package shows good agreement with FEM predictions.