Design and application trade-offs between high-density and high-speed ASICs

Two CMOS application-specific integrated circuit (ASIC) families are presented. The first ASIC family with 1.0 mu m channel length, is based on a sea-of-cells (SOC) architecture and a double-level-metal (DLM) structure. It offers chip density up to 100 K wirable circuits and higher I/O pin count using plastic-flat-pack (PFP) packaging. The second ASIC family with 0.5 mu m channel length offers up to 75 K wirable gates with boundary scan I/Os and array built-in self-test (ABIST). Single-chip-module (SCM), and multiple-chip-module (MCM) pin-in-hole packages are used to save space at the card level. Specific features are described, focusing on the complementarity offering of these two families and on the design tradeoffs between high-density and high-speed ASIC applications.< >