A 68MHz multi-channel all-digital programmable oscillator

A 68MHz programmable digitally-controlled oscillator (DCO) core is designed in 0.25 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the DCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used at higher frequencies by using faster FPGA devices or by implementing it in an advanced deep-submicron CMOS process.