Constraint identification for timing verification

Constraint identification for timing verification

A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, thou...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Grodstein, J.J., Pan, J., Grundmann, B., Gieseke, B., Yen, Y.T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Algorithm design and analysis
Analytical models
Circuit simulation
Clocks
Costs
Design automation
Latches
Logic devices
Robustness
Timing
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Beschreibung
Zusammenfassung:A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV.< >
DOI:10.1109/ICCAD.1990.129828