A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin

We present an implementation of a memory arbiter design that gives dynamic IP cores interfaced to multiple internal networks on the programmable chip concurrent access to multiple banks of the SRAM. The arbiter which uses a new fast version of round robin that we call idle skip, has a small instruct...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kearney, D.A., Veldman, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer interfaces Computer networks Concurrent computing Delay Field programmable gate arrays Memory management Network-on-a-chip Random access memory Read-write memory Round robin
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!