A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin

We present an implementation of a memory arbiter design that gives dynamic IP cores interfaced to multiple internal networks on the programmable chip concurrent access to multiple banks of the SRAM. The arbiter which uses a new fast version of round robin that we call idle skip, has a small instruction set which is invoked by applications allowing them to read and write multiple memory locations, read and write multiple memory locations in a streaming fashion and perform inter application communication with and without access to external SRAM. An atomic test and set instruction is provided that allows applications on the FPGA to lock regions of memory in arbitrary sized blocks to enable fine grained producer consumer style interaction between the dynamic IP cores and the host, and between dynamic IP cores of the FPGA.