Single-event effects in 0.18 /spl mu/m CMOS commercial processes

Single-event effects in 0.18 /spl mu/m CMOS commercial processes

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.

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Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on nuclear science 2003-12, Vol.50 (6), p.2135-2138
Hauptverfasser: Makihara, A., Sakaide, Y., Tsuchiya, Y., Arimitsu, T., Asai, H., Iide, Y., Shindou, H., Kuboyama, S., Matsuda, S.
Format: Artikel
Sprache:eng
Schlagworte:
Circuits
CMOS process
Epitaxial layers
Flip-flops
Foundries
Latches
Single event upset
Space technology
Substrates
Testing
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Beschreibung
Zusammenfassung:We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2003.821830