Package-silicon co-design-experiment with an SOC design
In this paper, we describe a package-silicon co-design approach attempted for an RF integrated SOC design. Extensive simulations were carried out to determine the sensitivity of different package layout parameters on signal integrity and noise related issues. These experiments helped in influencing...
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| creator | Suresh, P.R. Sundararajan, P.K. Goel, A. Udayakumar, H. Srinivasan, C. Sinari, V. Ravinutala, R. |
| description | In this paper, we describe a package-silicon co-design approach attempted for an RF integrated SOC design. Extensive simulations were carried out to determine the sensitivity of different package layout parameters on signal integrity and noise related issues. These experiments helped in influencing the package layout design and the custom I/O cell design. The I/O and core bump locations, and the package via locations were determined based on the reliability and noise considerations. Both the floorplanning and package layout were fine tuned to optimize the area and signal integrity issues. This was followed by extensive package simulations to determine the SSN and crosstalk numbers. |
| doi_str_mv | 10.1109/ICVD.2004.1260974 |
| format | Conference Proceeding |
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Extensive simulations were carried out to determine the sensitivity of different package layout parameters on signal integrity and noise related issues. These experiments helped in influencing the package layout design and the custom I/O cell design. The I/O and core bump locations, and the package via locations were determined based on the reliability and noise considerations. Both the floorplanning and package layout were fine tuned to optimize the area and signal integrity issues. This was followed by extensive package simulations to determine the SSN and crosstalk numbers.</description><identifier>ISBN: 0769520723</identifier><identifier>ISBN: 9780769520728</identifier><identifier>DOI: 10.1109/ICVD.2004.1260974</identifier><language>eng</language><publisher>Los Alamitos CA: IEEE</publisher><subject>Applied sciences ; Crosstalk ; Degradation ; Design optimization ; Design. Technologies. Operation analysis. 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Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Geometry</subject><subject>Integrated circuits</subject><subject>Packaging</subject><subject>Performance analysis</subject><subject>Radio frequency</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal analysis</subject><subject>Silicon</subject><subject>Switches</subject><isbn>0769520723</isbn><isbn>9780769520728</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1Lw0AQxRdEUGv_APGSi8eNs5_jHiV-FQoVLF7LZDOpqzUN2YL63xuI4LsMj_djmHlCXCgolYJwvahe70oNYEulPQS0R-IM0AenAbU5EfOc32GUCaisORX4TPGDtixz2qW474q4lw3ntO0kf_c8pE_uDsVXOrwV1BUvq6qY0nNx3NIu8_xvzsT64X5dPcnl6nFR3S5lcgCS3Y2PrTEYNFsHsUHgRtUWavRkPbrWmdCO1imgQAqtj9Go2gdde26cmYmraW1POdKuHaiLKW_68S4afjYKcXzOwMhdTlxi5v94qsD8AsYGT44</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Suresh, P.R.</creator><creator>Sundararajan, P.K.</creator><creator>Goel, A.</creator><creator>Udayakumar, H.</creator><creator>Srinivasan, C.</creator><creator>Sinari, V.</creator><creator>Ravinutala, R.</creator><general>IEEE</general><general>IEEE Computer Society</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>Package-silicon co-design-experiment with an SOC design</title><author>Suresh, P.R. ; Sundararajan, P.K. ; Goel, A. ; Udayakumar, H. ; Srinivasan, C. ; Sinari, V. ; Ravinutala, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i500-e586cf33792e450cd70ed1b40b76a4675f539f40b510a9a1746cc31b692b6ed53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Crosstalk</topic><topic>Degradation</topic><topic>Design optimization</topic><topic>Design. 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| identifier | ISBN: 0769520723 |
| ispartof | 17th International Conference on VLSI Design. Proceedings, 2004, p.531-536 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Crosstalk Degradation Design optimization Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Geometry Integrated circuits Packaging Performance analysis Radio frequency Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal analysis Silicon Switches |
| title | Package-silicon co-design-experiment with an SOC design |
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