Arsenic dimer implants for shallow extension in 0.13μm logic devices

Arsenic dimer implants for shallow extension in 0.13μm logic devices

Arsenic dimer, As 2 + , implants have been used for the formation of ultra-shallow source drain extensions for NMOS transistors in a 0.13 μm, 1.5 V CMOS logic process. A comparison of all electrical parameters including drive currents, sheet resistance, junction breakdown voltages and gate to drain...

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Hauptverfasser: Chang, B., Chang, J., Agarwal, A., Ameen, M.S., Reece, R.N., Chen, H.I., Chien, D., Tsai, C.C., Tsai, M., Weng, C.L., Wu, D.Y., Yang, C.K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
CMOS logic circuits
CMOS process
Contamination
Electric resistance
Implants
Logic devices
MOSFETs
Silicon
Throughput
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Zusammenfassung:Arsenic dimer, As 2 + , implants have been used for the formation of ultra-shallow source drain extensions for NMOS transistors in a 0.13 μm, 1.5 V CMOS logic process. A comparison of all electrical parameters including drive currents, sheet resistance, junction breakdown voltages and gate to drain capacitance indicate equivalent process performance for monomer and dimer implants. Arsenic dimer and monomer implants were also compared using bare silicon control wafers in both drift and decel mode. The dimer implants were found to be energy contamination free. The use of dimer implants resulted in machine throughput improvement of 4× without any adverse impact on the implanter performance in terms of ion source lifetime, particles, or implant uniformity.
DOI:10.1109/IIT.2002.1257951