A new fast and accurate method of extracting the parasitics of multi-layer packages

Due to the increase of portable and high performance integrated circuit (IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for complicated packages, a fast and ac...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Young-Soek Hong, Joon-Ho Choi, Chang-Woo Ko, Jin-Won Kim, Gi-Joung Jang, Moon-Hyun Yoo, Jeong-Taek Kong
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Chip scale packaging Computer aided engineering Electronics packaging Equivalent circuits Frequency Integrated circuit interconnections Integrated circuit packaging Lead Pins Power system interconnection
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