Family of folded bit-serial multipliers
The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functio...
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| container_end_page | 617 vol.2 |
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| creator | Ciric, V.M. Milentijevic, I.Z. Vojinovic, O.M. Tokic, T.I. |
| description | The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given. |
| doi_str_mv | 10.1109/TELSKS.2003.1246299 |
| format | Conference Proceeding |
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Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given.</description><identifier>ISBN: 0780379632</identifier><identifier>ISBN: 9780780379633</identifier><identifier>DOI: 10.1109/TELSKS.2003.1246299</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Delay ; Digital signal processing chips ; Elliptic curves ; Field programmable gate arrays ; Galois fields ; Public key cryptography ; Systolic arrays ; Throughput ; Very large scale integration</subject><ispartof>6th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service, 2003. 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TELSIKS 2003</btitle><stitle>TELSKS</stitle><date>2003</date><risdate>2003</risdate><volume>2</volume><spage>614</spage><epage>617 vol.2</epage><pages>614-617 vol.2</pages><isbn>0780379632</isbn><isbn>9780780379633</isbn><abstract>The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given.</abstract><pub>IEEE</pub><doi>10.1109/TELSKS.2003.1246299</doi></addata></record> |
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| identifier | ISBN: 0780379632 |
| ispartof | 6th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service, 2003. TELSIKS 2003, 2003, Vol.2, p.614-617 vol.2 |
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| language | eng |
| recordid | cdi_ieee_primary_1246299 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Delay Digital signal processing chips Elliptic curves Field programmable gate arrays Galois fields Public key cryptography Systolic arrays Throughput Very large scale integration |
| title | Family of folded bit-serial multipliers |
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