Family of folded bit-serial multipliers

Family of folded bit-serial multipliers

The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functio...

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Bibliographische Detailangaben
Hauptverfasser: Ciric, V.M., Milentijevic, I.Z., Vojinovic, O.M., Tokic, T.I.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Delay
Digital signal processing chips
Elliptic curves
Field programmable gate arrays
Galois fields
Public key cryptography
Systolic arrays
Throughput
Very large scale integration
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Beschreibung
Zusammenfassung:The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given.
DOI:10.1109/TELSKS.2003.1246299