A double precision floating point multiply

A double precision floating point multiply

A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply a...

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Bibliographische Detailangaben
Hauptverfasser: Montoye, R., Belluomini, W., Ngo, H., McDowell, C., Sawada, J., Nguyen, T., Veraa, B., Wagoner, J., Lee, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS logic circuits
CMOS technology
Inverters
Latches
Logic circuits
Logic devices
Power dissipation
Switches
Switching circuits
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Beschreibung
Zusammenfassung:A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply and 25/spl deg/C.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2003.1234323