A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the ener...

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Bibliographische Detailangaben
Hauptverfasser: Bougard, B., Giulietti, A., Derudder, V., Weijers, J.-W., Dupont, S., Hollevoet, L., Catthoor, F., Van der Perre, L., De Man, H., Lauwereins, R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Codecs
Communication standards
Concatenated codes
Convolutional codes
Energy consumption
Forward error correction
Interleaved codes
Iterative decoding
Throughput
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Beschreibung
Zusammenfassung:A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2003.1234245