Improved logic optimization using global flow analysis

Techniques for automatically reducing circuit size and improving testability are considered. Two extensions to a previously published method for circuit optimization based on ideas of global flow analysis are described. The first is a basic improvement in the primary results on which the earlier optimization was based; the second extends the applicability of the method to conditional optimizations as well. Together these enhancements result in improved performance for the original algorithm, as well as the ability to handle designer-specified don't cares and redundancy-removal uniformly in the framework of a graph-based synthesis system such as LSS.< >