High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub...

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Veröffentlicht in:IEEE transactions on electron devices 2003-09, Vol.50 (9), p.1961-1969
Hauptverfasser: Olsen, S.H., O'Neill, A.G., Driscoll, L.S., Kwa, K.S.K., Chattopadhyay, S., Waite, A.M., Tang, Y.T., Evans, A.G.R., Norris, D.J., Cullis, A.G., Paul, D.J., Robbins, D.J.
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Sprache:eng
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Zusammenfassung:Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2003.815603