90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology
This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF in...
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| creator | Jan, C.-H. Bielefeld, J. Buehler, M. Chikamane, V. Fischer, K. Hepburn, T. Jain, A. Jeong, J. Kielty, T. Kook, S. Marieb, T. Miner, B. Nguyen, P. Schmitz, A. Nashner, M. Scherban, T. Schroeder, B. Wang, P.-H. Wu, R. Xu, J. Zawadzki, K. Thompson, S. Bohr, M. |
| description | This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance. |
| doi_str_mv | 10.1109/IITC.2003.1219699 |
| format | Conference Proceeding |
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No.03TH8695)</title><addtitle>IITC</addtitle><description>This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. 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No.03TH8695)</btitle><stitle>IITC</stitle><date>2003</date><risdate>2003</risdate><spage>15</spage><epage>17</epage><pages>15-17</pages><isbn>9780780377974</isbn><isbn>0780377974</isbn><abstract>This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.</abstract><pub>IEEE</pub><doi>10.1109/IITC.2003.1219699</doi><tpages>3</tpages></addata></record> |
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| identifier | ISBN: 9780780377974 |
| ispartof | Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2003, p.15-17 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Assembly Atomic layer deposition Capacitance Clamps Compressive stress Dielectric constant Dielectric materials Packaging Plasma materials processing Thermal stresses |
| title | 90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology |
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