90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF in...

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Hauptverfasser: Jan, C.-H., Bielefeld, J., Buehler, M., Chikamane, V., Fischer, K., Hepburn, T., Jain, A., Jeong, J., Kielty, T., Kook, S., Marieb, T., Miner, B., Nguyen, P., Schmitz, A., Nashner, M., Scherban, T., Schroeder, B., Wang, P.-H., Wu, R., Xu, J., Zawadzki, K., Thompson, S., Bohr, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Assembly
Atomic layer deposition
Capacitance
Clamps
Compressive stress
Dielectric constant
Dielectric materials
Packaging
Plasma materials processing
Thermal stresses
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Beschreibung
Zusammenfassung:This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.
DOI:10.1109/IITC.2003.1219699