Analysis of bit transition count for EDAC encoded FSM

Analysis of bit transition count for EDAC encoded FSM

The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count wi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Venkateswaran, N., Balaji, V., Mahalingam, V., Rajaprabhu, T.L.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Educational institutions
Encoding
Error analysis
Error correction
Error correction codes
Fault detection
Fault tolerance
Hamming distance
Linear code
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.
DOI:10.1109/OLT.2003.1214391