Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In th...

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Bibliographische Detailangaben

Hauptverfasser:	Kandeepan, S., Reisenfeld, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Australia Cyclic redundancy check Frequency estimation Jitter Mathematical model Phase detection Phase locked loops Satellites Steady-state Systems engineering and theory
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