Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.