Fortuitous detection and its impact on test set sizes using stuck-at and transition faults
During manufacture testing, the maximum number of test patterns that can be applied is limited by the available amount of tester memory. This paper investigates the effect that the probability of fortuitous detection has on test pattern length when stuck-at and transition faults are targeted in four...
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| creator | Dworak, J. Wingfield, J. Cobb, B. Sooryong Lee Wang, L.-C. Mercer, M.R. |
| description | During manufacture testing, the maximum number of test patterns that can be applied is limited by the available amount of tester memory. This paper investigates the effect that the probability of fortuitous detection has on test pattern length when stuck-at and transition faults are targeted in four benchmark circuits. We show the magnitude of the increase in test pattern length that occurs when transition faults are targeted, and this indicates that current test pattern generation methods are not adequate to make multiple detections of timing faults practical for most circuits. |
| doi_str_mv | 10.1109/DFTVS.2002.1173514 |
| format | Conference Proceeding |
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| identifier | ISSN: 1550-5774 |
| ispartof | 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings, 2002, p.177-185 |
| issn | 1550-5774 2377-7966 |
| language | eng |
| recordid | cdi_ieee_primary_1173514 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Benchmark testing Circuit faults Circuit testing Electrical fault detection Fault detection Fault diagnosis Manufacturing System testing Test pattern generators Timing |
| title | Fortuitous detection and its impact on test set sizes using stuck-at and transition faults |
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