Control of the performance of polysilicon thin-film transistor by high-gate-voltage stress

Control of the performance of polysilicon thin-film transistor by high-gate-voltage stress

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases aft...

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Veröffentlicht in:IEEE electron device letters 1991-12, Vol.12 (12), p.676-678
Hauptverfasser: Dimitriadis, C.A., Coxon, P.A., Lowe, A.J., Stoemenos, J., Economou, N.A.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Artificial intelligence
Chemicals
Degradation
Electron mobility
Electronics
Exact sciences and technology
Grain boundaries
Hydrogen
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Stress control
Thin film transistors
Threshold voltage
Transistors
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Beschreibung
Zusammenfassung:The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO/sub 2/ interface.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.116952