Low power limiter [FET amplifiers]

Low power limiter [FET amplifiers]

The present article introduces the results of designing a low power limiter for GaAs FET amplifiers. The possibility of obtaining minimal values for the noise factor is shown when matching circuits are optimized with regard to the limiter diode parasitic capacitance and when the amplifying transisto...

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Bibliographische Detailangaben
Hauptverfasser: Krutov, A.V., Mitlin, V.A., Rebrov, A.S.
Format: Tagungsbericht
Sprache:eng ; rus
Schlagworte:
Gain
Gallium arsenide
Helium
HEMTs
IEEE catalog
Inductance
Microwave FETs
Microwave technology
Noise figure
Organizing
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Beschreibung
Zusammenfassung:The present article introduces the results of designing a low power limiter for GaAs FET amplifiers. The possibility of obtaining minimal values for the noise factor is shown when matching circuits are optimized with regard to the limiter diode parasitic capacitance and when the amplifying transistor gate-source junction is used as a detector diode.
DOI:10.1109/CRMICO.2002.1137181