Scalable Coherent Interface

The Scalable Coherent Interface Project (IEEE P1596) is establishing an interface standard for very-high-performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with up to 64K nodes. The P1596 Scalable Coherent Interface (SCI) will supply a peak bandwidth per node of 1 Gb/s. The SCI standard should facilitate assembly of processor, memory, I/O and bus bridge cards from multiple vendors into massively parallel systems with throughput far above what is possible today. The SCI standard encompasses two levels of interface, a physical level and a logical level. The physical level specifies electrical, mechanical and thermal characteristics of connectors and cards that meet the standard. The logical-level describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives and error recovery. Logical-level issues such as packet formats, packet transmission, transaction handshake, flow control, and cache coherence are addressed.< >