Packaging Technology for the NEC SX Supercomputer
Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 mega...
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| Veröffentlicht in: | IEEE transactions on components, hybrids, and manufacturing technology hybrids, and manufacturing technology, 1985-12, Vol.8 (4), p.462-467 |
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| container_end_page | 467 |
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| container_issue | 4 |
| container_start_page | 462 |
| container_title | IEEE transactions on components, hybrids, and manufacturing technology |
| container_volume | 8 |
| creator | Watari, T. Murano, H. |
| description | Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory. |
| doi_str_mv | 10.1109/TCHMT.1985.1136535 |
| format | Article |
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The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.</description><identifier>ISSN: 0148-6411</identifier><identifier>EISSN: 1558-3082</identifier><identifier>DOI: 10.1109/TCHMT.1985.1136535</identifier><identifier>CODEN: ITTEDR</identifier><language>eng</language><publisher>IEEE</publisher><subject>Cache memory ; Delay effects ; Integrated circuit technology ; Large scale integration ; Liquid cooling ; Logic ; National electric code ; Packaging machines ; Semiconductor device packaging ; Supercomputers</subject><ispartof>IEEE transactions on components, hybrids, and manufacturing technology, 1985-12, Vol.8 (4), p.462-467</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c331t-95fcd303c1376a7a682320fecda7bb8aaf6109bf24ff197b5e7c330fb52e8ce13</citedby><cites>FETCH-LOGICAL-c331t-95fcd303c1376a7a682320fecda7bb8aaf6109bf24ff197b5e7c330fb52e8ce13</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1136535$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1136535$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Watari, T.</creatorcontrib><creatorcontrib>Murano, H.</creatorcontrib><title>Packaging Technology for the NEC SX Supercomputer</title><title>IEEE transactions on components, hybrids, and manufacturing technology</title><addtitle>T-CHMT</addtitle><description>Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.</description><subject>Cache memory</subject><subject>Delay effects</subject><subject>Integrated circuit technology</subject><subject>Large scale integration</subject><subject>Liquid cooling</subject><subject>Logic</subject><subject>National electric code</subject><subject>Packaging machines</subject><subject>Semiconductor device packaging</subject><subject>Supercomputers</subject><issn>0148-6411</issn><issn>1558-3082</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1985</creationdate><recordtype>article</recordtype><recordid>eNpFj8tOwzAQRS0EEqHwA7DxD6R47NhxligqD6m0SA0SO8txx2mgbSInXfTvSWkkVqPR6My9h5B7YFMAlj0W-et7MYVMy2EXSgp5QSKQUseCaX5JIgaJjlUCcE1uuu6bMc4zxSICH9b92KreV7RAt9k326Y6Ut8E2m-QLmY5XX3R1aHF4Jpde-gx3JIrb7cd3o1zQj6fZ0N-PF--vOVP89gJAX2cSe_WggkHIlU2tUpzwZlHt7ZpWWprvRqKl54n3kOWlhLTAWS-lBy1QxATws9_XWi6LqA3bah3NhwNMHOSNn_S5iRtRukBejhDNSL-A-P1F95tUv0</recordid><startdate>19851201</startdate><enddate>19851201</enddate><creator>Watari, T.</creator><creator>Murano, H.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19851201</creationdate><title>Packaging Technology for the NEC SX Supercomputer</title><author>Watari, T. ; Murano, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c331t-95fcd303c1376a7a682320fecda7bb8aaf6109bf24ff197b5e7c330fb52e8ce13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1985</creationdate><topic>Cache memory</topic><topic>Delay effects</topic><topic>Integrated circuit technology</topic><topic>Large scale integration</topic><topic>Liquid cooling</topic><topic>Logic</topic><topic>National electric code</topic><topic>Packaging machines</topic><topic>Semiconductor device packaging</topic><topic>Supercomputers</topic><toplevel>online_resources</toplevel><creatorcontrib>Watari, T.</creatorcontrib><creatorcontrib>Murano, H.</creatorcontrib><collection>CrossRef</collection><jtitle>IEEE transactions on components, hybrids, and manufacturing technology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Watari, T.</au><au>Murano, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Packaging Technology for the NEC SX Supercomputer</atitle><jtitle>IEEE transactions on components, hybrids, and manufacturing technology</jtitle><stitle>T-CHMT</stitle><date>1985-12-01</date><risdate>1985</risdate><volume>8</volume><issue>4</issue><spage>462</spage><epage>467</epage><pages>462-467</pages><issn>0148-6411</issn><eissn>1558-3082</eissn><coden>ITTEDR</coden><abstract>Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.</abstract><pub>IEEE</pub><doi>10.1109/TCHMT.1985.1136535</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0148-6411 |
| ispartof | IEEE transactions on components, hybrids, and manufacturing technology, 1985-12, Vol.8 (4), p.462-467 |
| issn | 0148-6411 1558-3082 |
| language | eng |
| recordid | cdi_ieee_primary_1136535 |
| source | IEEE |
| subjects | Cache memory Delay effects Integrated circuit technology Large scale integration Liquid cooling Logic National electric code Packaging machines Semiconductor device packaging Supercomputers |
| title | Packaging Technology for the NEC SX Supercomputer |
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