Packaging Technology for the NEC SX Supercomputer

Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.