A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter

This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, cross-coupled cascode connection, and close-loop poles placement. MOS switches are driven by bootstrapping circuits that do not subject the devices to large, terminal voltages. The circuit layout is being completed and the chip will be fabricated in a 0.5-/spl mu/m CMOS technology. Simulation results have been checked for all process corners and including the effect of 3/spl sigma/ capacitor mismatch, comparator offset, 10% variation in poly-poly capacitor size and temperature varying from 0/spl deg/C to 70/spl deg/C. The results show that the converter has differential nonlinearity (DNL) of less than 0.4LSB and achieves 59.1 dB SNDR for 19.9 MHz sinusoidal inputs. Power consumption is estimated at 30.5 mW.