Area efficient current steering DAC using current tuning

Area efficient current steering DAC using current tuning

A 10 bit segmented (5+5 bit) high speed current steering DAC is presented in this paper. Devices with small area are used to reduce the total area without affecting linearity. A current tuning loop is suggested to overcome the sizing mismatch error. The master slave concept is used along with this t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Sunil Rafeeque, K.P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog circuits
Calibration
Clocks
Decoding
Frequency conversion
Linearity
Master-slave
Signal resolution
Switches
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 10 bit segmented (5+5 bit) high speed current steering DAC is presented in this paper. Devices with small area are used to reduce the total area without affecting linearity. A current tuning loop is suggested to overcome the sizing mismatch error. The master slave concept is used along with this to generate multiple copies of weighted current sources. Sizing reduces the area requirement to 20% of the 2/sup n/ unit cell design. The tuning reduces the DNL and INL to 0.1 LSB without considering any random error.
DOI:10.1109/APCCAS.2002.1115066