A High-Efficiency Crosstalk Control Method of the Staggered High-Speed via Array in PCB for Chiplet-Based System

In this research, a high-efficiency crosstalk control method of the staggered high-speed via array in printed circuit board for Chiplet-based system is developed based on the neural network (NN) model and particle swarm optimization (PSO) algorithm. Based on the high frequency structure simulator (HFSS) and Q3D software, the simulation results of the staggered high-speed via array are obtained. The complex relationship among the structural parameters, crosstalk indexes, and characteristic impedance of the staggered high-speed via array is described by NN model. Then, the structural parameters of the staggered high-speed via array are optimized by PSO algorithm according to the multiobjective function including eight crosstalk indexes and eight characteristic impedance indexes. According to the optimized structural parameters, the effectiveness is verified through the finite element simulation. The simulated indexes agree with the desired indexes. In the four cases, the maximum error between the simulated and optimized indexes is 2.00%, which indicates that the developed method can accurately optimize the structural parameters of the staggered high-speed via array to control the crosstalk and characteristic impedance. Therefore, the developed high-efficiency design method can achieve the performance indexes control of the staggered high-speed via array, which can improve the performance of Chiplet-based system.