Analysis and Suppression of Harmonic Deteriorations Related to a Few-Submodule and Low-Switching-Frequency MMC-Based UPFC

System efficiency, power quality, and economic benefits have always been essential for the Unified Power Flow Controller (UPFC based on a Modular Multilevel Converter (MMC). This paper proposes a low-switching-frequency MMC-UPFC operation scheme based on the carrier phase shift pulse width modulation (CPS-PWM), which can significantly reduce switching loss and improve system efficiency. However, in medium-voltage MMC applications, the number of sub-modules in the UPFC is usually small (less than 30) exacerbating the harmonic distortions in the MMC-UPFC and reducing the switching frequency further deteriorates harmonics and increases capacitor voltage ripple. Therefore, to address the increased capacitor voltage ripple caused by low switching frequency, this paper proposes a reasonable carrier ratio (FR) design method. Analyzing and suppressing the capacitor voltage ripple at low switching frequencies can maintain capacitor voltage stability while significantly reducing the switching frequency. To address the issue of increased harmonics due to low switching frequency and few sub-modules, this paper combines the FR design method with an active LLCL filter method. An improved genetic algorithm is used to establish an objective function related to switching frequency harmonics and total inductance value, which can suppress a large number of high-order harmonics remaining from the CPS-PWM scheme, reduce the total inductance value, and compare this method with the single L filtering scheme widely used in UPFC engineering planning. Simulation on PLECS software verifies the effectiveness of the proposed method.