Elevated-Epi (Elepi) Technique for 3D IC With Stacked FinFETs, Interlevel Metal, and 25×33 mm2 Single-Crystalline Silicon on SiO2

The elevated-epi technique (EET) is introduced for fabricating single-crystal (100) silicon of wafer field size ( 25\times 33 mm) for monolithic 3-D integrated circuits (3D ICs) using a low substrate temperature pulse laser method. This method enables the demonstration of 3-D inverters with interlayer metal M0 positioned between two layers of FinFETs. Additionally, a hybrid-3-D cell library is presented to enhance the performance, power, and area (PPA) of 3D IC. This hybrid-3-D cell library is crucial in design-technology co-optimization, significantly improving PPA metrics for advanced 3D IC applications.