Excellent Endurance (> 1013) of Charge Trap Memory Based on HxWO3 Charge Trap Layer With Shallow Trap Level Using Hydrogen Spillover
In this study, we present an IGZO-based volatile charge trap memory, employing a hydrogenated WO 3 (H x WO _{{3}}\text {)} charge trap layer (CTL) with shallow traps. To overcome the interfacial issues in conventional Si-based transistors, we utilized the IGZO transistor to facilitate fast charge t...
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| Veröffentlicht in: | IEEE electron device letters 2024-10, Vol.45 (10), p.1804-1807 |
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| container_title | IEEE electron device letters |
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| creator | Han, Geonhui Kim, Jaeseon Kim, Youngdong Seo, Jongseon Lee, Donghwa Hwang, Hyunsang |
| description | In this study, we present an IGZO-based volatile charge trap memory, employing a hydrogenated WO 3 (H x WO _{{3}}\text {)} charge trap layer (CTL) with shallow traps. To overcome the interfacial issues in conventional Si-based transistors, we utilized the IGZO transistor to facilitate fast charge trapping / de-trapping within the CTL without barrier. Furthermore, through the hydrogen spillover with chemical reaction, we engineered the trap level and density in WO x based CTL to achieve the shallow trap levels. Consequently, for the shallow trap level, high hydrogen concentration (>10%) was realized in the CTL owing to low activation energy with hydrogen spillover. In addition, both experimental results and Density Functional Theory simulations confirmed that hydrogen interstitial defects (H _{\text {i}}\text {)} could serve as shallow traps ( |
| doi_str_mv | 10.1109/LED.2024.3443087 |
| format | Article |
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To overcome the interfacial issues in conventional Si-based transistors, we utilized the IGZO transistor to facilitate fast charge trapping / de-trapping within the CTL without barrier. Furthermore, through the hydrogen spillover with chemical reaction, we engineered the trap level and density in WO x based CTL to achieve the shallow trap levels. Consequently, for the shallow trap level, high hydrogen concentration (>10%) was realized in the CTL owing to low activation energy with hydrogen spillover. In addition, both experimental results and Density Functional Theory simulations confirmed that hydrogen interstitial defects (H<inline-formula> <tex-math notation="LaTeX">_{\text {i}}\text {)} </tex-math></inline-formula> could serve as shallow traps (<0.1 eV) in the H x WO 3 CTL when the hydrogen concentration exceeded 10% in the WO 3 bulk. Finally, the synergy effect between the IGZO transistor and H<inline-formula> <tex-math notation="LaTeX">_{{0}.{18}} </tex-math></inline-formula> WO 3 CTL enabled low voltage operation (<2 V), fast switching speed (<10 ns), highly stable endurance (<inline-formula> <tex-math notation="LaTeX">\gt 10^{{13}} </tex-math></inline-formula> cycles), large sensing margin (>3 V), multi-bit operation (3 bit), and excellent retention (<inline-formula> <tex-math notation="LaTeX">\sim ~20 </tex-math></inline-formula> s).]]></description><identifier>ISSN: 0741-3106</identifier><identifier>DOI: 10.1109/LED.2024.3443087</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Capacitorless DRAM ; charge trap memory ; Electron traps ; Electrons ; Hydrogen ; Random access memory ; Sensors ; spillover method ; Transistors ; trap level ; volatile memory</subject><ispartof>IEEE electron device letters, 2024-10, Vol.45 (10), p.1804-1807</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0002-8956-3648 ; 0000-0002-5135-9350 ; 0000-0003-1930-1914 ; 0009-0002-0699-9241</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10634566$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10634566$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Han, Geonhui</creatorcontrib><creatorcontrib>Kim, Jaeseon</creatorcontrib><creatorcontrib>Kim, Youngdong</creatorcontrib><creatorcontrib>Seo, Jongseon</creatorcontrib><creatorcontrib>Lee, Donghwa</creatorcontrib><creatorcontrib>Hwang, Hyunsang</creatorcontrib><title>Excellent Endurance (> 1013) of Charge Trap Memory Based on HxWO3 Charge Trap Layer With Shallow Trap Level Using Hydrogen Spillover</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description><![CDATA[In this study, we present an IGZO-based volatile charge trap memory, employing a hydrogenated WO 3 (H x WO<inline-formula> <tex-math notation="LaTeX">_{{3}}\text {)} </tex-math></inline-formula> charge trap layer (CTL) with shallow traps. To overcome the interfacial issues in conventional Si-based transistors, we utilized the IGZO transistor to facilitate fast charge trapping / de-trapping within the CTL without barrier. Furthermore, through the hydrogen spillover with chemical reaction, we engineered the trap level and density in WO x based CTL to achieve the shallow trap levels. Consequently, for the shallow trap level, high hydrogen concentration (>10%) was realized in the CTL owing to low activation energy with hydrogen spillover. In addition, both experimental results and Density Functional Theory simulations confirmed that hydrogen interstitial defects (H<inline-formula> <tex-math notation="LaTeX">_{\text {i}}\text {)} </tex-math></inline-formula> could serve as shallow traps (<0.1 eV) in the H x WO 3 CTL when the hydrogen concentration exceeded 10% in the WO 3 bulk. Finally, the synergy effect between the IGZO transistor and H<inline-formula> <tex-math notation="LaTeX">_{{0}.{18}} </tex-math></inline-formula> WO 3 CTL enabled low voltage operation (<2 V), fast switching speed (<10 ns), highly stable endurance (<inline-formula> <tex-math notation="LaTeX">\gt 10^{{13}} </tex-math></inline-formula> cycles), large sensing margin (>3 V), multi-bit operation (3 bit), and excellent retention (<inline-formula> <tex-math notation="LaTeX">\sim ~20 </tex-math></inline-formula> s).]]></description><subject>Annealing</subject><subject>Capacitorless DRAM</subject><subject>charge trap memory</subject><subject>Electron traps</subject><subject>Electrons</subject><subject>Hydrogen</subject><subject>Random access memory</subject><subject>Sensors</subject><subject>spillover method</subject><subject>Transistors</subject><subject>trap level</subject><subject>volatile memory</subject><issn>0741-3106</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpVjs1Pg0AUxPegibV69-DhHfUA7vL2g15MtKI1wfTQNj02W3hQDAWyYC13_3BJ7MXTZCa_mQxjN4L7QvDJQxy9-AEPpI9SIg_NGRtxI4WHgusLdtm2n5wLKY0csZ_omFBZUtVBVKVfzlYJwd0jCC7wHuoMpjvrcoKlsw180L52PTzbllKoK5gd13P8R8S2JwfrotvBYmfLsv4-5XSgElZtUeUw61NX51TBoikG4kDuip1ntmzp-qRjtnqNltOZF8_f3qdPsVcMx7vh_laTRmtVamyaZdxgFgShxMHKUIdKkp0ESm1VGBAmiksyKU6GilZkNOKY3f7tFkS0aVyxt67fDNsoldb4C4fZW8Q</recordid><startdate>202410</startdate><enddate>202410</enddate><creator>Han, Geonhui</creator><creator>Kim, Jaeseon</creator><creator>Kim, Youngdong</creator><creator>Seo, Jongseon</creator><creator>Lee, Donghwa</creator><creator>Hwang, Hyunsang</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><orcidid>https://orcid.org/0000-0002-8956-3648</orcidid><orcidid>https://orcid.org/0000-0002-5135-9350</orcidid><orcidid>https://orcid.org/0000-0003-1930-1914</orcidid><orcidid>https://orcid.org/0009-0002-0699-9241</orcidid></search><sort><creationdate>202410</creationdate><title>Excellent Endurance (> 1013) of Charge Trap Memory Based on HxWO3 Charge Trap Layer With Shallow Trap Level Using Hydrogen Spillover</title><author>Han, Geonhui ; Kim, Jaeseon ; Kim, Youngdong ; Seo, Jongseon ; Lee, Donghwa ; Hwang, Hyunsang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i106t-31b6e63aa5d7adff073f22843d7a486854ea9255b582e3c504e7d39e6365e7633</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Annealing</topic><topic>Capacitorless DRAM</topic><topic>charge trap memory</topic><topic>Electron traps</topic><topic>Electrons</topic><topic>Hydrogen</topic><topic>Random access memory</topic><topic>Sensors</topic><topic>spillover method</topic><topic>Transistors</topic><topic>trap level</topic><topic>volatile memory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Han, Geonhui</creatorcontrib><creatorcontrib>Kim, Jaeseon</creatorcontrib><creatorcontrib>Kim, Youngdong</creatorcontrib><creatorcontrib>Seo, Jongseon</creatorcontrib><creatorcontrib>Lee, Donghwa</creatorcontrib><creatorcontrib>Hwang, Hyunsang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Han, Geonhui</au><au>Kim, Jaeseon</au><au>Kim, Youngdong</au><au>Seo, Jongseon</au><au>Lee, Donghwa</au><au>Hwang, Hyunsang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Excellent Endurance (> 1013) of Charge Trap Memory Based on HxWO3 Charge Trap Layer With Shallow Trap Level Using Hydrogen Spillover</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2024-10</date><risdate>2024</risdate><volume>45</volume><issue>10</issue><spage>1804</spage><epage>1807</epage><pages>1804-1807</pages><issn>0741-3106</issn><coden>EDLEDZ</coden><abstract><![CDATA[In this study, we present an IGZO-based volatile charge trap memory, employing a hydrogenated WO 3 (H x WO<inline-formula> <tex-math notation="LaTeX">_{{3}}\text {)} </tex-math></inline-formula> charge trap layer (CTL) with shallow traps. To overcome the interfacial issues in conventional Si-based transistors, we utilized the IGZO transistor to facilitate fast charge trapping / de-trapping within the CTL without barrier. Furthermore, through the hydrogen spillover with chemical reaction, we engineered the trap level and density in WO x based CTL to achieve the shallow trap levels. Consequently, for the shallow trap level, high hydrogen concentration (>10%) was realized in the CTL owing to low activation energy with hydrogen spillover. In addition, both experimental results and Density Functional Theory simulations confirmed that hydrogen interstitial defects (H<inline-formula> <tex-math notation="LaTeX">_{\text {i}}\text {)} </tex-math></inline-formula> could serve as shallow traps (<0.1 eV) in the H x WO 3 CTL when the hydrogen concentration exceeded 10% in the WO 3 bulk. Finally, the synergy effect between the IGZO transistor and H<inline-formula> <tex-math notation="LaTeX">_{{0}.{18}} </tex-math></inline-formula> WO 3 CTL enabled low voltage operation (<2 V), fast switching speed (<10 ns), highly stable endurance (<inline-formula> <tex-math notation="LaTeX">\gt 10^{{13}} </tex-math></inline-formula> cycles), large sensing margin (>3 V), multi-bit operation (3 bit), and excellent retention (<inline-formula> <tex-math notation="LaTeX">\sim ~20 </tex-math></inline-formula> s).]]></abstract><pub>IEEE</pub><doi>10.1109/LED.2024.3443087</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-8956-3648</orcidid><orcidid>https://orcid.org/0000-0002-5135-9350</orcidid><orcidid>https://orcid.org/0000-0003-1930-1914</orcidid><orcidid>https://orcid.org/0009-0002-0699-9241</orcidid></addata></record> |
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| subjects | Annealing Capacitorless DRAM charge trap memory Electron traps Electrons Hydrogen Random access memory Sensors spillover method Transistors trap level volatile memory |
| title | Excellent Endurance (> 1013) of Charge Trap Memory Based on HxWO3 Charge Trap Layer With Shallow Trap Level Using Hydrogen Spillover |
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