A configurable ROM circuit for use in gate arrays
A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate arra...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1987-02, Vol.22 (1), p.117-118 |
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| container_end_page | 118 |
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| container_issue | 1 |
| container_start_page | 117 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 22 |
| creator | Ueda, M. Sakashita, K. Arakawa, T. Okazaki, K. Asai, S. Kuramitsu, Y. |
| description | A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate array, based on a gate-isolated cell configuration, employing 1.5-/spl mu/m double-metal CMOS technology. The 16-bit /spl times/ 64-word ROM in the processor saves 30% of the transistor area due to the DWM-ROM. |
| doi_str_mv | 10.1109/JSSC.1987.1052683 |
| format | Article |
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| ispartof | IEEE journal of solid-state circuits, 1987-02, Vol.22 (1), p.117-118 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Automatic testing Built-in self-test CMOS technology Decoding Electronics Exact sciences and technology Logic arrays Logic testing Programmable logic arrays Read only memory Solid state circuits Storage and reproduction of information Very large scale integration |
| title | A configurable ROM circuit for use in gate arrays |
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