A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and compa...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1981-10, Vol.16 (5), p.499-505
Hauptverfasser:	Chao, H.H., Dennard, R.H., Tsai, M.Y., Wordeman, M.R., Cramer, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Capacitors DRAM chips Electrodes FETs Implants Isolation technology Noise reduction Random access memory Testing
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